The present invention relates to an inverter or switching circuit making use of complementary insulated gate field effect transistors (hereinafter abbreviated as CMOSFET's). More particularly, it relates to an inverter circuit with a capacitive load connected to the output terminal thereof in which a heavy transient current flows from a power supply under a transient condition where an input signal is changed to invert the inverter output.
Since an inverter circuit using CMOSFET's (hereinafter abbreviated as CMOS inverter) consumes little power in the steady state condition, its use in large-scale integrated circuits (thereinafter abbreviated as IC) is desirable. Under the transient condition, however, a considerably large power supply current (hereinafter abbreviated as I.sub.DD) flows through the CMOS inverter due to a charging current flowing to a capacitive component of the load. Accordingly, the peak value of I.sub.DD in the CMOS inverter is large during the transient period. Therefore, it is necessary to take measures, such as lowering the impedance of power supply wirings to the CMOS inverter to reduce this transient current. But such a measure would deteriorate a valuable feature of the CMOS circuit; namely, that it can use fine wirings because of the low steady state power consumption. This problem becomes more remarkable in a memory IC where a large number of address inverters operate simultaneously. For instance, in a 64K-bit memory, an address input is 16-bits, which means that at least 16 address inverters operate simultaneously in response to 16 address input signals applied in parallel. In that case, I.sub.DD is multiplied by a factor of 16, causing an extremely large peak current to flow from the power supply of this memory IC. Consequently, a noise is generated in the power supply lines, causing many faults in the operation of the memory IC.
It has been proposed to reduce the peak current by prolonging the CMOS inverter switching time to thereby gradually charge the load capacitance. However, this method has a drawback that speed-up of the whole IC is prevented because of the prolonged response time of the inverter.